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ASIP designers use parallelism and specialization to achieve this optimization, while trying to retain full C programmability. Parallelism enables designs to run multiple functions at once, and its three main forms can be applied individually or in combination to boost performance.
The options are laid out in Figure 2 and described here. Instruction-level parallelism uses an orthogonal instruction set, as in very long instruction word VLIW architectures, or an encoded instruction set which delivers the operational parallelism needed without the overhead associated with VLIW architectures.
Data-level parallelism implements vector processing, which involves applying one instruction to multiple data items. Figure 2 Design options — parallelism Source: Synopsys.
Designers can also define application-specific data types and interfaces. Figure 3 depicts various forms of specialization. Figure 3 Design options — specialization Source: Synopsys. Designers therefore need to be able to rapidly explore the impact of architectural choices upon their ASIP, by doing three things:.
Designers need a quick and easy way to define a candidate architecture, ideally using a modelling approach that avoids specifying deep implementation details early in the design process. Designers also need software tools to map benchmark code onto the candidate architectures, and, since it is impractical to develop a new toolchain for each candidate architecture manually, this needs to be automated.
Design exploration involves evaluating each candidate architecture against the defined benchmarks. There are two main ways of doing this. Compiler-in-the-loop: Designers need to use a compiler to run benchmarks onto each candidate architecture, rather than trying to use time-consuming and error-prone assembly language.
The C compiler, ISS and profiler can be combined with a debugger, assembler, and linker to form a full software development toolkit SDK. The SDK should be available early in the design process and quickly retargetable to the various architectural alternatives, to enable efficient design-space exploration.
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Advertise with us. Hide details. Abstract : The application-specific instruction set processors ASIPs have received more and more attention in recent years. ASIPs make trade-offs between flexibility and performance by extending the base instruction set of a general-purpose processor with custom functional units CFUs.
Custom instructions, executed on CFUs, make it possible to improve performance and achieve flexibility for extensible processors. The custom instruction synthesis flow involves two essential issues: custom instruction enumeration subgraph enumeration and custom instruction selection subgraph selection.
However, both enumerating all possible custom instructions of a given data-flow graph and selecting the most profitable custom instructions from the enumerated custom instructions are computationally difficult problems.