Quantum computing for communications : an engineering approach

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One approach splits the plane into two parts. The second part is a scalable custom hardware. The challenge is in creating scalable custom hardware that is fast enough and can scale with machine size, and in creating the right high-level instruction abstraction. The control processor plane operates at a low level of abstraction: it converts compiled code to commands for the control and measurement layer. As a result, a user will not interact with or need to understand the control processor plane directly.

Rather, the user will interact with a host computer. This plane will attach to that computer and act to accelerate the execution of some applications. The host processor is a classical computer, running a conventional operating system with standard supporting libraries for its own operation. This computing system provides all of the software development tools and services users expect from a computer system.

Attaching a quantum processor to a classical computer allows it to utilize all of its features without needing to start entirely from scratch. The rest of this chapter reviews the current candidate qubit technology choices upon which to base a quantum computer. For the two furthest developed quantum technologies, superconducting and trapped ion qubits, this discussion includes details of the qubit and control planes in use in prototypical computers at the time of publication of this report , the current challenges that must be overcome for each technology, and an assessment of the prospects for scale-up to very.

The review of other emerging technologies provides a sense of their current status, and potential advantages if they are developed further. The first quantum logic gate was demonstrated in using trapped atomic ions [ 1 ], following a theoretical proposal earlier in the same year [ 2 ]. Since the original demonstration, technical advances in qubit control have enabled experimental demonstration of fully functional processors at small scale and implementation of a wide range of simple quantum algorithms.

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Despite success in small-scale demonstrations, the task of constructing scalable and quantum computers considered viable by current computing industry standards out of trapped ions remains a significant challenge. Unlike the very large scale integration VLSI of transistors enabled by the integrated circuit IC , building a quantum computer based upon trapped ion qubits requires integration of technologies from a wide range of domains, including vacuum, laser, and optical systems, radio frequency RF and microwave technology, and coherent electronic controllers [ 3 - 5 ].

A path to a viable quantum computer must address these integration challenges. A trapped ion quantum data plane comprises the ions that serve as qubits and a trap that holds them in specific locations. Appendix B provides a technical overview of current strategies for constructing a trapped ion quantum data plane and its associated control and measurement plane. Based on the high-fidelity component operations demonstrated to date, small-scale ion trap systems have been assembled where a universal set of quantum logic operations can be implemented on a qubit system in a programmable manner [ 6 - 9 ], forming the basis of a general-purpose quantum computer.

Not surprisingly, at percent for two-qubit gates, the error rates of individual quantum logic operations in these fully functional qubit systems lag behind the 10 —2 to 10 —3 range [ 10 , 11 ] for state-of-the-art demonstrations of two-qubit systems, pointing to the challenge of maintaining the high fidelity across all qubits as the system.

Nonetheless, the versatility of these prototype systems has enabled a variety of quantum algorithms and tasks to be implemented on them. All of the prototype general-purpose trapped-ion quantum computer systems demonstrated to date consist of a chain of 5 to 20 static ions in a single potential well.

In these machines, each single qubit gate operation takes 0.

Each ion in the chain interacts with every other ion in the chain due to the strong Coulomb interaction in a tight trap through motional degree of freedom that is shared among the ions. This interaction can be leveraged to realize quantum logic gates between nonadjacent ions, leading to dense connectivity among the qubits in a single ion chain. An alternative approach is to induce a two-qubit gate between an arbitrary pair of ions in the chain by illuminating specific ions with tightly focused and carefully tailored control signals, such that only the desired ions move—many control signals are used to make the force on all the other ions cancel out [ 19 ].

Using either approach, one can realize a general-purpose quantum processor with fully connected qubits [ 20 ], meaning that two-qubit gates may be implemented between arbitrary pairs of qubits in the system [ 21 ]; these capabilities are expected to scale to over 50 qubits in a relatively straightforward way [ 22 ].

It is likely that some early, small-scale quantum computers qubits based on ion traps will become available by the early s. Like current machines, these early demonstration systems are likely to consist of a single chain of ions and feature unique all-to-all connectivity among the qubits in the chain, efficiently implementing any quantum circuit with arbitrary circuit structures. However, many conceptual and technical challenges remain toward a creating a truly scalable, fault-tolerant ion trap quantum computer. Examples of such challenges include the difficulty of isolating individual ion motions as chain length increases, the number of ions one can individually address with gate laser beams, and measuring individual qubits.

Further scaling of trapped ion quantum computers to well beyond the sizes necessary for demonstrating quantum supremacy. Such shuttling requires a complex trap with multiple controllable electrodes. Because the quantum information is stored in the internal states of the ion, which have been shown to be unaffected by shuttling between chains in small experiments, this approach does not contribute to any detectable decoherence [ 24 ]. Recent adoption of semiconductor microfabrication techniques has enabled the design and construction of highly complex ion traps, which are now routinely used for sophisticated shuttling procedures.

This technology could potentially be used to connect multiple ion chains on a single chip, enabling for an increase in scale—provided that the controllers necessary to manipulate these qubits can be integrated accordingly. Even if this ion shuttling is successful on a single chip, eventually the system will need to be scaled up further. Two approaches are currently being explored: photonic interconnections, and tiling chips.

A strategy for connecting multiple qubit subsystems into a much larger system is to use quantum communication channels. One viable approach involves preparing one of the ions in a subsystem in a particular excited state and inducing it to emit a photon in such a way that the quantum state of the photon for example, its polarization or frequency is entangled with the ion qubit [ 25 , 26 ]. When both output ports simultaneously record detection of a photon [ 27 ], it signals that the two ions that generated the photons have been prepared in a maximally entangled state [ 28 , 29 ].

This protocol entangles a pair of ion qubits across two chips, without the ion qubits ever directly interacting with each other. Although the protocol must be attempted many times until it succeeds, its successful execution is heralded by an unmistakable signature both detectors registering photons , and can be used deterministically in ensuing computational tasks—for example, to execute a two-qubit gate acting across chips [ 30 ].

This protocol was indeed demonstrated first in trapped ions [ 31 ] followed by other physical platforms [ 32 - 34 ]. Given the continued improvement.

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This approach opens up the possibility of using existing photonic networking technology, such as large optical cross-connect switches [ 37 ], to connect hundreds of ion trap subsystems into a network of modular, parallel quantum computers [ 38 - 40 ]. An alternative approach to the scaling beyond a single-ion trap chip is to tile all-electrical trap subsystems to create a system where ions from one ion trap chip can be transferred to another chip [ 41 ].

This shuttling across different integrated circuits requires careful alignment of shuttling channels and special preparation of the boundaries of these integrated circuits, which has not yet been demonstrated. In this proposal, all qubit gates are carried out by microwave fields and magnetic field gradients, free from the off-resonant spontaneous scattering and stability challenges associated with the use of laser beams [ 42 ]. While this integration approach remains entirely speculative at this point, this approach has the potential benefit of relying only on mature microwave technology and electrical control for the critical quantum logic gates, rather than using lasers and optics, which require much higher precision components.

For trapped ions, necessary technology developments toward scalable quantum computer systems include the ability to fabricate ion traps with higher levels of functionality, assemble stabilized laser systems with adequate control, deliver electromagnetic EM fields that drive the quantum gates either microwave or optical to the ions with sufficient levels of precision to affect only the qubit being targeted preferably allowing multiple operations at a time , detect the qubit states in parallel without disturbing the data qubits, and program the control EM fields that manipulate the ion qubits so that the overall system achieves sufficient fidelity for the practical application needs.

If these challenges are met, one will be able to take advantage of the strengths in trapped ions: some of the best performances of all physical systems in representing a single qubit, thanks to the fact that these qubits are fundamentally identical as opposed to those which are manufactured , and the high fidelity of qubit operations at small experimental scales.

Like current silicon integrated circuits, superconducting qubits are lithographically defined electronic circuits. Their compatibility with. Appendix C provides a technical overview of current strategies for constructing a superconductor quantum data plane and its associated control and measurement plane. In the context of digital quantum computation and quantum simulations, the present state-of-art for operational gate error rate is better than below 0. Based on these developments, superconducting qubit circuits with around 10 qubits have been engineered to demonstrate prototype quantum algorithms [ 48 , 49 ] and quantum simulations [ 50 , 51 ], prototype quantum error detection [ 52 - 55 ], and quantum memories [ 56 ], and, as of , cloud-based 5-, , and qubit circuits are available to users worldwide.

However, the error rates are higher in these larger machines—for example, the 5-qubit machines available on the Web in have gate error rates of around 5 percent [ 57 , 58 ].

In the context of quantum annealing, commercial systems exist with over 2, qubits and integrated cryogenic control based on classical superconducting circuitry [ 59 , 60 ]. These are the largest qubit-based systems currently available, with two orders of magnitude times more qubits than current gate-based QCs.

Solutions for Redundancy-Free Error Correction in Quantum Channel | SpringerLink

To achieve this scale machine required careful design trade-offs and significant engineering effort. The decision to integrate the control electronics with the qubits enabled D-Wave to rapidly scale the number of qubits in their system, but also results in the qubits being built in a more lossy material. They purposely traded off qubit fidelity for an easier scaling path.

Thus, the coherence times of the qubits in these machines are over 3 orders of magnitude worse than those in current gate-based machines, although this is expected to be less of a limitation for quantum annealers than for gate-based machines. Progress in gate-based machines has emphasized the optimization of qubit and gate fidelities, at sizes limited to on the order of tens of qubits. Since the first demonstration of a superconducting qubit in , the qubit coherence time T 2 in gate-level machines has improved more than five orders-of-magnitude, standing at around microseconds today. This remarkable improvement in coherence arose from reducing energy losses in the qubit through advances in materials science, fabrication engineering, and qubit design by groups worldwide.

The current approach, using room temperature control and measurement planes, with multiple wires per qubit, should scale to around 1, physical qubits [ 61 ]. This section reviews the factors that cause this limit, and then discusses what is currently known about the path to even larger machines. Many factors will limit the size of machine that can be achieved by simply scaling up the number of qubits placed on a single integrated circuit. These include the following:. This areal connection will need three-dimensional 3D integration schemes using flip-chip bump-bonding and superconducting through-silicon vias, technologies that are being developed to connect high-coherence qubit chips with multilayer interconnect routing wafers [ 63 , 64 ].

First, qubit fidelities need to be improved to provide the lower error rates needed to support practical quantum error correction.

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In addition, as the size of the computer increases to millions of qubits and beyond, advanced process monitoring, statistical process control, and new methods for reducing defects relevant to high-coherence devices will be required to assess and improve qubit yield. Just as fabrication tools have been specialized to target specific, advanced complementary metal-oxide semiconductor CMOS processes, it is likely that specialized tools that target specific qubit-fabrication processes will need to be developed to enhance yield and minimize fabrication-induced defects that cause decoherence.

Wafer real estate is another consideration for larger machines. Assuming qubit unit cells with repeat distance critical dimensions of 50 microns state-of-the-art today [ 65 ], a large integrated circuit of 20 mm by 20 mm. If one used an entire mm wafer for one processor, the wafer could hold around , qubits. While that is sufficient for the near future, reducing the qubit unit cell critical dimension while retaining coherence and controllability will increase qubit density and enable larger numbers of qubits on a single mm wafer.

Moving to wafer-size integrated circuits requires creating a new package. The qubits are generally around 5 GHz, which corresponds to a free-space wavelength of around 60 mm. The wavelength is further reduced in the presence of dielectrics like the silicon wafer. Using the rule of thumb that a clean microwave environment requires dimensions less than one-quarter of a wavelength, it is clear that further research is needed before large high-quality packages can be built.

Controlling more than a thousand qubits will require a new strategy for the control and measurement plane. This control logic will need to be introduced using either 3D integration to connect the qubit plane with this local control plane or fabricated monolithically but must be done so without compromising qubit coherence and gate fidelity.

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